Freescale Semiconductor /MK60F15 /SIM /SOPT2

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Interpret as SOPT2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)USBHSRC 0 (0)RTCCLKOUTSEL 0 (000)CLKOUTSEL 0 (00)FBSL 0 (0)CMTUARTPAD 0 (0)TRACECLKSEL 0 (0)NFC_CLKSEL 0 (00)PLLFLLSEL 0 (0)USBF_CLKSEL 0 (00)TIMESRC 0 (00)USBFSRC 0 (00)ESDHCSRC 0 (00)NFCSRC

CMTUARTPAD=0, NFCSRC=00, USBF_CLKSEL=0, NFC_CLKSEL=0, TRACECLKSEL=0, FBSL=00, TIMESRC=00, USBFSRC=00, CLKOUTSEL=000, RTCCLKOUTSEL=0, ESDHCSRC=00, USBHSRC=00, PLLFLLSEL=00

Description

System Options Register 2

Fields

USBHSRC

USB HS clock source select

0 (00): Bus clock

1 (01): MCGPLL0CLK

2 (10): MCGPLL1CLK

3 (11): OSC0ERCLK

RTCCLKOUTSEL

RTC clock out select

0 (0): RTC 1 Hz clock drives RTC CLKOUT.

1 (1): RTC 32 kHz oscillator drives RTC CLKOUT.

CLKOUTSEL

Clock out select

0 (000): FlexBus clock (reset value)

2 (010): Flash ungated clock

3 (011): LPO clock (1 kHz)

4 (100): MCGIRCLK

5 (101): RTC 32 kHz clock

6 (110): OSC0ERCLK

7 (111): OSC1ERCLK

FBSL

Flexbus security level

0 (00): All off-chip accesses (op code and data) via the FlexBus are disallowed.

2 (10): Off-chip op code accesses are disallowed. Data accesses are allowed.

3 (11): Off-chip op code accesses and data accesses are allowed.

CMTUARTPAD

CMT/UART pad drive strength

0 (0): Single-pad drive strength for CMT IRO or UART0_TXD.

1 (1): Dual-pad drive strength for CMT IRO or UART0_TXD.

TRACECLKSEL

Debug trace clock select

0 (0): MCGCLKOUT

1 (1): Core/system clock

NFC_CLKSEL

NFC Flash clock select

0 (0): Clock divider NFC clock

1 (1): EXTAL1 clock.

PLLFLLSEL

PLL/FLL clock select

0 (00): MCGFLLCLK

1 (01): MCGPLL0CLK

2 (10): MCGPLL1CLK

3 (11): System Platform clock

USBF_CLKSEL

USB FS clock select

0 (0): External bypass clock (PTE26)

1 (1): Clock divider USB FS clock

TIMESRC

Ethernet timestamp clock source select

0 (00): System platform clock

1 (01): MCGPLLCLK/MCGFLLCLK selected by PLLFLLSEL[1:0]

2 (10): OSC0ERCLK

3 (11): External bypass clock (PTE26)

USBFSRC

USB FS clock source select

0 (00): MCGPLLCLK/MCGFLLCLK selected by PLLFLLSEL[1:0]

1 (01): MCGPLL0CLK

2 (10): MCGPLL1CLK

3 (11): OSC0ERCLK

ESDHCSRC

ESDHC perclk source select

0 (00): Core/system clock

1 (01): MCGPLLCLK/MCGFLLCLK selected by PLLFLLSEL[1:0]

2 (10): OSC0ERCLK

3 (11): External bypass clock (PTD11)

NFCSRC

NFC Flash clock source select

0 (00): Bus clock

1 (01): MCGPLL0CLK

2 (10): MCGPLL1CLK

3 (11): OSC0ERCLK

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